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Altera_Forum
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13 years ago

ISP 1761 VHDL USB Peripheral Controller Timing Issues

Hi Altera Forum Members, I am currently Designing on the Terasic DE4 with a Stratix IV EP4SGX230 and Quartus 12.1SP1(formerly just 12.1) for my Master Thesis. I have no experience with the Nios...
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Altera_Forum
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13 years ago

Thank you for your help rbugalho.

As I'm running out of time, I fixed this Problem by modifying my HAL entity. It now runs with 100MHz and setup states for CS_n, ADR and a hold state after WE_n goes high. The core now runs without any Timing constraints.