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Altera_Forum
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13 years ago

ISP 1761 VHDL USB Peripheral Controller Timing Issues

Hi Altera Forum Members, I am currently Designing on the Terasic DE4 with a Stratix IV EP4SGX230 and Quartus 12.1SP1(formerly just 12.1) for my Master Thesis. I have no experience with the Nios...
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Altera_Forum
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13 years ago

Hmm, that goes a bit over my TQ kung fu but at least one detail: the target of the generated clocks that you're using for the constrains should be the FPGA pin (get_ports something), not an internal register.