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Altera_Forum's avatar
Altera_Forum
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9 years ago

Is this metastability or is this Signaltap behaviour normal?

Hi there

I am experiencing strange behaviour from SignalTap. Occasionally, when I read data, the data return seems garbled and impossible. The values are strange for the registers from which they originate and state machines transition to unusual states, however, the device continues to function normally and as designed. Is it possible that the data being displayed by signaltap is somehow incorrect or corrupted, or is this definitely metastability that recovers every time? It seems strange to me to be metastability because when I try to trigger on the abnormal data, it never triggers, and I do not have stability issues with the device. This seems to indicate that the SignalTap data is perhaps being corrupted in the chain somehow. Is it possible for that to happen?

I have attached an image showing an example. The area between the two green bars is valid data, the rest seems nonsensical and impossible (I realise it is not possible to understand what is going on without knowledge of the design, but take my word for it.) The device continued to function normally after this, as every other time.

Thanks in advance.http://www.alteraforum.com/forum/attachment.php?attachmentid=12898&stc=1

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Because the values are like this for many cycles, I highly doubt it is anything to do with signaltap, and more what your design is actually doing. Why it works I have no idea as we dont have access to the design.

    I do note though - this is a very large signal tap capture - why so many signals? are you trying to verify the design using signaltap? do you have a full set of testbenches for the design?
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    Because the values are like this for many cycles, I highly doubt it is anything to do with signaltap, and more what your design is actually doing. Why it works I have no idea as we dont have access to the design.

    I do note though - this is a very large signal tap capture - why so many signals? are you trying to verify the design using signaltap? do you have a full set of testbenches for the design?

    --- Quote End ---

    Thanks for your reply Tricky.

    I am sceptical as to it being the design as some of the bits that are shown to be changed, should never change, but I did want someone else's opinion. Additionally, I can never trigger on the changes as shown, which tells me that either it's an extremely strange coincidence, or logic is simply never seeing the signals in that way. The signals are largely there for functional verification. There is not a test bench for the design at this stage.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    Thanks for your reply Tricky.

    I am sceptical as to it being the design as some of the bits that are shown to be changed, should never change, but I did want someone else's opinion. Additionally, I can never trigger on the changes as shown, which tells me that either it's an extremely strange coincidence, or logic is simply never seeing the signals in that way. The signals are largely there for functional verification. There is not a test bench for the design at this stage.

    --- Quote End ---

    Signaltap is not a verification tool - it is a debug tool.

    I highly suggest you get a testbench up and running - debugging a problem like this in signaltap is very slow.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Are you clocking it in the correct domain? That's the most common one. (Naturally, if it's not toggling at all then it doesn't matter what domain.) The other possibility I can think of is the stp domain is not meeting timing. Very unlikely though, as it's very simple logic. I don't think I've ever seen it fail.

    One other thing is to duplicate some of the registers in our logic(and put an attribute on not to remove fanout free registers), then tap those too and see if they match. Just a thought.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    If the JTAG connection is affected by electrical interferences, signaltap data is likely to be corrupted. Reloading it with ReadData button can assure that the displayed waveform is stable.