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Because the values are like this for many cycles, I highly doubt it is anything to do with signaltap, and more what your design is actually doing. Why it works I have no idea as we dont have access to the design.
I do note though - this is a very large signal tap capture - why so many signals? are you trying to verify the design using signaltap? do you have a full set of testbenches for the design?
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Thanks for your reply Tricky.
I am sceptical as to it being the design as some of the bits that are shown to be changed, should never change, but I did want someone else's opinion. Additionally, I can never trigger on the changes as shown, which tells me that either it's an extremely strange coincidence, or logic is simply never seeing the signals in that way. The signals are largely there for functional verification. There is not a test bench for the design at this stage.
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