Is this metastability or is this Signaltap behaviour normal?

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Thanks for your reply Tricky.

I am sceptical as to it being the design as some of the bits that are shown to be changed, should never change, but I did want someone else's opinion. Additionally, I can never trigger on the changes as shown, which tells me that either it's an extremely strange coincidence, or logic is simply never seeing the signals in that way. The signals are largely there for functional verification. There is not a test bench for the design at this stage.

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Signaltap is not a verification tool - it is a debug tool.

I highly suggest you get a testbench up and running - debugging a problem like this in signaltap is very slow.