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krieg's avatar
krieg
Icon for New Contributor rankNew Contributor
7 years ago
Solved

Is there an SDC/TCL command for returning the clock associated with a logic cell?

In Vivado, I can do this with

set myreg [get_cells -hierarchihcal myregister]
set myreg_clk [get_clocks -of_objects $myreg]

The Quartus version of get_clocks does not seem to have the -of_objects argument. Has anyone figured out a way to get the clock associated with a logic cell?

A little background: I have a design that uses multiple clock domains and I want to be able to add constraints based on the clock periods. In Vivado, I wrote a constraints file that does this for all instances of my design within the top-level design. I am trying to do the same in Quartus.

I am using Quartus Prime Pro 18.0.

  • krieg's avatar
    krieg
    7 years ago

    Taking inspiration from sstrell's answer, I was able to solve this.

    The code below is an excerpt from my initial success. It has not yet been tested with multiple designs.

    # get all clocks
set clks [all_clocks]
# get the register that I want to constrain
set my_reg [get_cells -hierarchical *myregistername]
# get all fanins to my register (use -stop_at_clock so it doesn't go all the way back to the master clock)
set fanins [get_fanins -clock -stop_at_clocks [get_object_info -name $my_reg]]
# find which fanin is a clock pin
foreach_in_collection fanin $fanins {
   if {[get_object_info -type $fanin] == "pin"} {
      if {[get_pin_info -is_clock_pin $fanin]} {
         set clkpin $fanin
      }
   }
}
# get the clock pin net ID
set clknet [get_pin_info -net $clkpin]
# compare the clock pin net ID to each clock in the design; get the period of the clock that matches
foreach_in_collection clk $clks {
   if {[get_object_info -name [get_clock_info -targets $clk]] == [get_object_info -name $clknet]} {
      set clkperiod [get_clock_info -period $clk]
   }
}

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    When you create the clock constraints themselves in your .sdc file, you define the period. There's no need that I see to know what logic the clock is driving. That's set up in your design itself.

    I guess you could use the get_fanouts collection (not standard SDC) to create a collection of all the logic driven by a clock. Something like this:

    set myreg_clk [get_fanouts [get_pins pll|outclk] -through [get_pins -hierarchical *|clk]]

    So whatever registers have this PLL clock output driven into the registers' clk input will be included in the collection. Is that what you're looking for?

    #iwork4intel

    • krieg's avatar
      krieg
      Icon for New Contributor rankNew Contributor
      7 years ago

      Thanks for your reply.

      I agree with your first statement. There is no need to know what logic my clocks are driving. Allow me to explain more about what I am trying to do.

      My design is intended for reuse and will be implemented in many top-level designs, all with potentially different clocking schemes. I am writing a constraints file that any future user of my design can add to his/her project. It needs to correctly apply constraints based on the top-level design's clock domains. For this reason, the constraints file needs to be agnostic to the top-level design's clocking scheme.

      So I am not trying to determine which registers are driven by each clock. Rather I am trying to determine which clock is driving a specific register.

      I think it may be possible to accomplish this with what you suggested. It would go something like this:

      • Get the register that I want to constrain
      • Get a list of all clocks in the top-level design
      • Get a list of all registers driven by each clock
      • Match my register to one of the lists (now I know which clock drives my register)

      This would be several lines of code (as opposed to the two lines that it took in Vivado). I'm hoping there is a simpler solution to this, but I think that this would get the job done. If you have any more suggestions based on what I wrote here, I would be happy to hear them. Either way, I will post my final solution so that others can possibly benefit from it.

      • krieg's avatar
        krieg
        Icon for New Contributor rankNew Contributor
        7 years ago

        Taking inspiration from sstrell's answer, I was able to solve this.

        The code below is an excerpt from my initial success. It has not yet been tested with multiple designs.

        # get all clocks
set clks [all_clocks]
# get the register that I want to constrain
set my_reg [get_cells -hierarchical *myregistername]
# get all fanins to my register (use -stop_at_clock so it doesn't go all the way back to the master clock)
set fanins [get_fanins -clock -stop_at_clocks [get_object_info -name $my_reg]]
# find which fanin is a clock pin
foreach_in_collection fanin $fanins {
   if {[get_object_info -type $fanin] == "pin"} {
      if {[get_pin_info -is_clock_pin $fanin]} {
         set clkpin $fanin
      }
   }
}
# get the clock pin net ID
set clknet [get_pin_info -net $clkpin]
# compare the clock pin net ID to each clock in the design; get the period of the clock that matches
foreach_in_collection clk $clks {
   if {[get_object_info -name [get_clock_info -targets $clk]] == [get_object_info -name $clknet]} {
      set clkperiod [get_clock_info -period $clk]
   }
}