Is there an SDC/TCL command for returning the clock associated with a logic cell?

Taking inspiration from sstrell's answer, I was able to solve this.

The code below is an excerpt from my initial success. It has not yet been tested with multiple designs.

# get all clocks
set clks [all_clocks]
# get the register that I want to constrain
set my_reg [get_cells -hierarchical *myregistername]
# get all fanins to my register (use -stop_at_clock so it doesn't go all the way back to the master clock)
set fanins [get_fanins -clock -stop_at_clocks [get_object_info -name $my_reg]]
# find which fanin is a clock pin
foreach_in_collection fanin $fanins {
   if {[get_object_info -type $fanin] == "pin"} {
      if {[get_pin_info -is_clock_pin $fanin]} {
         set clkpin $fanin
      }
   }
}
# get the clock pin net ID
set clknet [get_pin_info -net $clkpin]
# compare the clock pin net ID to each clock in the design; get the period of the clock that matches
foreach_in_collection clk $clks {
   if {[get_object_info -name [get_clock_info -targets $clk]] == [get_object_info -name $clknet]} {
      set clkperiod [get_clock_info -period $clk]
   }
}