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Altera_Forum's avatar
Altera_Forum
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12 years ago

Is there a way to reducethe ressource usage of QSYS interconnects?

Hi,

as time passed, my design grew and grew. In the meantime its ressource usage on my 4C75 is 85% or 63.600 LEs.

I noticed that 58.000 LEs are needed by my QSYS-System and within this 3.400 LEs are needed by "QSYS_mm_interconnect_0" and 47.800 LEs are needed by "QSYS_mm_interconnect_1".

That means about 80% of the design ressources are needed only for the QSYS interconnects.

I think I'm doing something terribly wrong.......

My QSYS-System consists of a PCIe-HIP as MM-Master with two BARs:

BAR2 contains the mSGDMA-Core and the Read- and Write-Masters to some FiFos.

BAR0 contains everything else like a bunch of PIOs (about 40 to 50), Tristate Conduit and other Memory-Controllers.

I don't want to speed up BAR0, because there are no timing critical devices on it. But I wonder if there is a way to reduce the Ressource-Usage.

I tried to use this: http://www.altera.com/literature/hb/qts/qsys_optimize.pdf but the examples for reducing Logic have multiple Masters. I only have one Master per BAR.

Does anyone know some help?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Well, I'm sorry I have to answer this by myself:

    There is a way: I implemented four MM-Pipeline-Bridges to my QSYS-Design and made also four groups of PIOs. Each of the Groups has an continous Adress-Range (no other ip in between). I disconnected the PIOs from the BAR, connected them to the Pipeline-Bridges and calculated their addresses to match the old design.

    Then I compiled the whole Design an voilla, now my design uses 18.000LEs less!!!! Hurayyyy!!

    The reason: In the original Design every PIO had its own Burst-Adapter to convert the 512Byte Bursts from PCIe-HIP to 4Byte Bursts to PIO.

    With the Bridge there is only one Burst-Adapter between PCIe-HIP and Bridge. Between the Bridge and the PIOs ther is no further Adapter nessesary becaus it is already converted to 4Byte Bursts.

    And an additional success: The timing of my design was improved by 2ns!!!

    Yours

    Steffen
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Great Job.

    Not only did you fix the issue yourself, you understand why it improved the design, and explained it for the community. +1!

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    It would be easier to spot these things if qsys actually showed you the bridges.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thats the best: QSYS does show you the Adapters, but you have to activate it first:

    Goto: Tools -> Options -> Internal and check: "Enable internal Features"

    This gives you an extra Menue called "Internal". In this Menue there is "Show Adapter Reports". This gives you a view (in Text) of all additional Adapters implemented by QSYS. This also helps you to group the right IPs together.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Just to bring this thread upto date in case anyone stumbles across it. As of Quartus15.x you can view the Qsys system with all the normally hidden interconnect by selecting System->Show System With Qsys Interconnect. Sadly you are unable to do much of anything useful with this additional insight to help teach Qsys the errors of its ways.