Is there a way to reducethe ressource usage of QSYS interconnects?

Well, I'm sorry I have to answer this by myself:

There is a way: I implemented four MM-Pipeline-Bridges to my QSYS-Design and made also four groups of PIOs. Each of the Groups has an continous Adress-Range (no other ip in between). I disconnected the PIOs from the BAR, connected them to the Pipeline-Bridges and calculated their addresses to match the old design.

Then I compiled the whole Design an voilla, now my design uses 18.000LEs less!!!! Hurayyyy!!

The reason: In the original Design every PIO had its own Burst-Adapter to convert the 512Byte Bursts from PCIe-HIP to 4Byte Bursts to PIO.

With the Bridge there is only one Burst-Adapter between PCIe-HIP and Bridge. Between the Bridge and the PIOs ther is no further Adapter nessesary becaus it is already converted to 4Byte Bursts.

And an additional success: The timing of my design was improved by 2ns!!!

Yours

Steffen