Forum Discussion
The VHDL written FPGA fabric master has multiple AvalonMM master ports that are connected to multiple peripherals which are shared with a Nios that also connects to them. When the FPGA fabric master wants to perform a read/write it shall take the base address of the desired peripheral and add the offset for the register to be accessed. This information is available to the Nios from System.h file. How does a fabric based master get it? The base addresses should exist in a VHDL package version of the System.h which can be included into the VHDL of the custom fabric master. I hope it is more clear why I need this.
In Qsys we have a tab for "address map". I just need this information to be put into a VHDL package automatically when compilation starts!
Intel provides no solution for this.