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gyuunyuu's avatar
gyuunyuu
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5 years ago

Is there a standard way to extract the base addresses in sopc info file into a VHDL file?

For an FGPA fabric AvalonMM master, it is very important that the base addresses be correctly defined in a HDL source file so it can make use of them. The base addresses can change easily as we make ...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Hassan,


In plarform designer, once you assign base address, interconnect, etc, the HDL generated (verilog or VHDL) which is the output, there would be address, interconnect component, top level in it. If there is changes in base address in sopinfo, reassign the address and generate the HDL again.


Thanks,

Regards


  • gyuunyuu's avatar
    gyuunyuu
    Icon for Contributor rankContributor
    5 years ago

    I have design a custom fabric master that needs to know the base address of each peripheral before it can access them. The base addresses would come from a package. This custom fabric master is written in VHDL and will have multiple Avalon master ports connected to different peripherals.

    Which Qsys automatically generated VHDL file stores the base address for each peripheral connected to each AvalonMM master port of the RTL based FPGA fabric master? I have not found it yet.