Is Quartus Prime really support VHDL 2008?

​According to "Intel Quartus Prime Support for VHDL 2008" (https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vhdl/vhdl_list_2008_vhdl_support.htm), Quartus supports some subset of VHD 2008.

However, it seems that the implementation is not correct.

According to Section 9.2.3, result of STD_ULOGIC ?= STD_ULOGIC should STD_ULOGIC. However, the following code snippet failed to compile with error 10327: can't determine definition of operator ""?="" -- found 0 possible definitions

-- synthesis VHDL_INPUT_VERSION VHDL_2008
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity demo is
	port (
		a: in std_ulogic;
		b: in std_ulogic;
		r: out std_ulogic
	);
end;
 
architecture rtl of demo is
begin
	r <= a ?= b;
end;

Modifying type of r to boolean elimates error.

Moreover, in the VHDL-2008, STD_LOGIC_VECTOR is subtype of STD_ULOGIC_VECTOR, and STD_ULOGIC_VECTOR is one-dimensional array type whose element is std_ULOGIC. Therefore, STD_LOGIC_VECTOR ?= STD_LOGIC_VECTOR should be defined. However, the following snippet also failed with similar error:

-- synthesis VHDL_INPUT_VERSION VHDL_2008
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity demo is
	port (
		a: in std_logic_vector(3 downto 0);
		b: in std_logic_vector(3 downto 0);
		r: out boolean
	);
end;
 
architecture rtl of demo is
begin
	r <= a ?= b;
end;

Modifying type of a and b to std_ulogic_vector elimates error.

I'm using Quartus Prime Lite version 18.0.0

As I don't have Pro license, I also want to ask whether the Pro version can compile these code snippet without error.