Is it possible to use ALTLVDS_RX processing single ended signals in Cyclone V GX?

@sYimi​ , I see, so you really are resource limited (as you clearly stated at the outset :-) ). There are not enough PLL's to do it the straightforward way.

Hopefully ALTDDIO_IN will work for you. So long as the clock/data pair from each FPGA is properly aligned, you should be able to make it work.

If you control both sides, any chance you could do it with transceivers instead of LVDS (I think you have 9) Would actually use fewer pins, but you'll have PLL issues ...

Maybe someone else will have a better idea.