ContributorHi,
I wrote a personal IP which will send IRQ to HPS(Liunx) in some situation.
I'm planning to write the LKM to use that IRQ.
But parameter setting confused me a lot.
Could you guys explain the IRQ sender settings for me?
What are they? How they should be set to what purpose?
Why there is the clock and reset selection, what's the purpose of that?
Where can I find these setting information?
Thanks.
reguards.
ContributorAnd as I select none to every select the Platform Designer gave me the following warning:
any one knows how to fix that?
Regular ContributorHi
I have consulted the engineering team on this information.
I will update you when there is new information from the engineering team.
Regards
Jingyang, Teh
Regular ContributorHi
There is still no reply from engineering team.
However I have asked around my senior colleagues of mine and they said that one to two clock cycle of the periphclk should be sufficient.
The interrupt signal is a conduit of 32 bits length associating to 0 to 31 of the interrupt number.
Regards
Jingyang, Teh
ContributorHi,
Thank you for your help,
but still I don't understand the settings mean.
Looking forward to the engineering department official reply on explaining the what these settings do.
Reguards.
Regular ContributorHi Alex
You could refer to the document in the link below for more details on the signals:
Regards
Jingyang, Teh
ContributorHi,
In that case, it says it's the name of linked Avalon-mm port name.
And if I put the irq signal to the f2h_irq directly, do I need to set the Avalon MM name,clock and reset signals?
If it must, is that the Avalon MM pipeline bridge my_timer connected to?
Regular ContributorHi Alex
For the "Interrupt Sender Properties", it is the minimum required signals that needs to be present in your custom IP.
If you refer to the timer IP, the timer IP there is a reset input signal, clock input signal, avalon input signal and interrupt output signal.
You could leave the avalon signals unconnected, it should be able to run.
It is required to access the register or set settings from the avalon master.
Regards
Jingyang, Teh
ContributorHi,
For my custom IP, I set some inputs as well:
input: 16bit control register, 16bit timer flag register
output: 16bit timer irq signal.
Please correct me if Im wrong:
In that case, if I want to control the timer in my usersapce & kernel space, I have to use Avalon MM bridge.
And my interrupt setting(the sender setting in platform designer) can be keep blanked?
Thank you
Reguards.
Regular ContributorHi Alex
The Interrupt sender setting is referring to the input signal that you have.
input: 16bit control register, 16bit timer flag register
The signals are associated to the interrupt.
Like it is required as part of the interrupt. E.g. after interrupt you would either get data or set data to the IP.
The clock are required to sink the communication between the HPS and IP.
You need to use the Avalon MM to communicate between HPS and IP.
Regards
Jingyang, Teh
ContributorHi,
In that case, in the IP interrupt sender setting,
my "Associated addressble interface" should be my IP master(which is a Avalon MM bridge),
then what's the "offset" and "bridges to receiver" stands for?
Reguards.
Regular ContributorHI Alex
The offset refers to the split bytes of the Avalon Slave.
In the table the host is a 32 bit long where as the slave is 8 bit long.
There will be 4 packets of data from the slave to the host.
Regards
Jingyang, Teh
Regular ContributorHi Alex
Any update on this case?
Regards
Jingyang,Teh
