Introducing delay between output pins

Hi,

I want my EPM570 to act as a ring counter and demultiplexer that distributes incoming data to 8 connected devices sequentially. To do that I use a ring counter as an output clock and pass data trough register to output. The problem is that the connected device requires 0.5ns setup time and 1.5ns hold time. Is it possible to ensure this requirement in Quartus?

So far I wrote the following Verilog code (simplified):

module RingCounter(
	input clk,
	input rst,
	input data_in,
	output reg [7:0] counter,
	output reg data_out
);

always @(posedge clk)
begin
	if (rst)
		counter <= {{7{1'b0}}, 1'b1};
	else
		counter <= {counter[6:0], counter[7]};
	data_out <= data_in;
end


endmodule

And tried to add the following constraints

create_clock -name clock -period 8.33 [get_ports {clk}]
derive_pll_clocks


set_output_delay -clock { clock } -reference_pin [get_ports {counter[0]}]  -min -0.5 [get_ports {data_out}]
set_output_delay -clock { clock } -reference_pin [get_ports {counter[0]}]  -max 1.5 [get_ports {data_out}]

But these constraints produce an error:

Reference pin counter[0] is invalid. It is not clocked by the clock specified in set_input_delay/set_output_delay's -clock option.

As I understand, this error is due to the fact that input clock is not connected directly to none of the outputs (though it obviously drives the counter register). But I don't know how to change my constraints/design to fit above-mentioned requirements.

Any help would be appreciated