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emptysamurai's avatar
emptysamurai
Icon for New Contributor rankNew Contributor
4 years ago

Introducing delay between output pins

Hi,

I want my EPM570 to act as a ring counter and demultiplexer that distributes incoming data to 8 connected devices sequentially. To do that I use a ring counter as an output clock and pass data trough register to output. The problem is that the connected device requires 0.5ns setup time and 1.5ns hold time. Is it possible to ensure this requirement in Quartus?

So far I wrote the following Verilog code (simplified):

module RingCounter(
	input clk,
	input rst,
	input data_in,
	output reg [7:0] counter,
	output reg data_out
);

always @(posedge clk)
begin
	if (rst)
		counter <= {{7{1'b0}}, 1'b1};
	else
		counter <= {counter[6:0], counter[7]};
	data_out <= data_in;
end


endmodule

And tried to add the following constraints

create_clock -name clock -period 8.33 [get_ports {clk}]
derive_pll_clocks


set_output_delay -clock { clock } -reference_pin [get_ports {counter[0]}]  -min -0.5 [get_ports {data_out}]
set_output_delay -clock { clock } -reference_pin [get_ports {counter[0]}]  -max 1.5 [get_ports {data_out}]

But these constraints produce an error:

Reference pin counter[0] is invalid. It is not clocked by the clock specified in set_input_delay/set_output_delay's -clock option.

As I understand, this error is due to the fact that input clock is not connected directly to none of the outputs (though it obviously drives the counter register). But I don't know how to change my constraints/design to fit above-mentioned requirements.

Any help would be appreciated

3 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Your output delay constraints don't make sense. You're sort of creating a source synchronous output with counter[0] as the clock, but counter[0] is a data path, not a clock path, for SDC, and it's not based on another clock in the design, as is required for a clock constraint like create_generated_clock.

    I guess your best bet would be to set up a relationship between clk (assuming the PLL output clock is not used for this) and counter[0] with a generated clock constraint so perhaps:

    create_generated_clock -name clk_out -source [get_ports clk] [get_ports counter[0]] -divide_by 8

    set_output_delay -clock [get_clocks clk_out] -min -0.5 [get_ports {data_out}]

    set_output_delay -clock [get_clocks clk_out] -max 1.5 [get_ports {data_out}]

    And normally you would also need this so the path is not analyzed as a data path:

    set_false_path -to [get_ports counter[0]]

    Does that work?

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      4 years ago

      We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.