Introducing delay between output pins

Your output delay constraints don't make sense. You're sort of creating a source synchronous output with counter[0] as the clock, but counter[0] is a data path, not a clock path, for SDC, and it's not based on another clock in the design, as is required for a clock constraint like create_generated_clock.

I guess your best bet would be to set up a relationship between clk (assuming the PLL output clock is not used for this) and counter[0] with a generated clock constraint so perhaps:

create_generated_clock -name clk_out -source [get_ports clk] [get_ports counter[0]] -divide_by 8

set_output_delay -clock [get_clocks clk_out] -min -0.5 [get_ports {data_out}]

set_output_delay -clock [get_clocks clk_out] -max 1.5 [get_ports {data_out}]

And normally you would also need this so the path is not analyzed as a data path:

set_false_path -to [get_ports counter[0]]

Does that work?