internal osc timing const

Question

using the internal osc 80mhz "altint_osc" ip then divide by 2 to drive my logic, but it output warning  even after i put the clk constrain.  any help?

create_clock -name int_clk -period 25ns   [get_ports {frequency_divider:frequency_divider_inst|clk_div2}] 
clk_div2 is output reg
 i also try get_pins &amp; drive_clock_uncertainty didnt help with the warning
Warning (332060): Node: frequency_divider:frequency_divider_inst|clk_div2 was determined to be a clock but was found without an associated clock assignment.

sstrell · Answer

You don't mention which device, but an internal clock gets constrained with create_generated_clock, not create_clock.

kennyt_altera · Answer

Is this oscillator? you may take a look inhttps://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd01222015_416.html

s002wjh · Answer

for some reason get_pins doesn't work.  i had to use get_registers for my divider to set timing

kennyt_altera · Answer

thanks, good to know this.

kennyt_altera · Answer

Since this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Forum Discussion

internal osc timing const

5 Replies

Recent Discussions

Quartus did not start

The quartus license works with version 25.0 but not with version 17.0

Docker image for Quartus Pro 26.1 missing ?

Timing analysis - long combinational path

timing violation fix