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s002wjh's avatar
s002wjh
Icon for New Contributor rankNew Contributor
5 years ago

internal osc timing const

using the internal osc 80mhz "altint_osc" ip then divide by 2 to drive my logic, but it output warning even after i put the clk constrain. any help? create_clock -name int_clk -period 25ns [ge...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Since this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.