Forum Discussion
s002wjh
New Contributor
5 years agointernal osc timing const
using the internal osc 80mhz "altint_osc" ip then divide by 2 to drive my logic, but it output warning even after i put the clk constrain. any help?
create_clock -name int_clk -period 25ns [ge...
KennyT_altera
Super Contributor
5 years agoIs this oscillator? you may take a look in
s002wjh
New Contributor
5 years agofor some reason get_pins doesn't work. i had to use get_registers for my divider to set timing