Interfacing Verilog design with NIOS using External Clock

Hi

I am working on Altera DE3 board with Strartix III FPGA. Verilog part of my design is capturing LVDS data from the HSTC Ports and deserializing the 8 channels of data on port. two channels (other than 8) provide the clocking. One is frame clock where each frame has 12 bits (i couldnt use deserilaizing mega function coz its 10 bits). other clock is the bit clock where 1 bit has to be read on each edge (falling and rising), giving us 6 cycles of bit clock per frame. these clocks are coming from an ADC board connected at HSTC and the data rate can be changed any time using the functionalities of board. That is why i have to use the clock from board for all my processing. i have successfully deserialized the data from 8 channels and stored it on 8 onchip RAMS ( 8 channels). me n my partner also have a nios application designed which can communicate with a PC via USB link. for now it is just creating incremental numbers and sending them.

Coming to the problem, now the target is to send the deserilized data of 8 channels stored in onchip RAM of FPGA to PC using NIOS USB application. i have never worked with Verilog-NIOS interface before so my question might be very stupid. doing some reading on this forum i found out that i can use FIFOs and Scatter-Gather DMA to somehow send data to Avalon BUS. Can some1 explain it to me a bit more or refer to a detailed document or thread. also how do i make sure that NIOS works insync with the clock i am fetching externally. i do not want any samples to be missed or sent more than once due to speed mismatch. The ADC can provide 10 to 50 Mega Samples per second and ofc NIOS should somehow adjust itself to this speed. if you have reached this point, thank you for your patience while reading all this and i hope you will be able to help.

Regards

Omar