Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Interfacing Verilog design with NIOS using External Clock

Hi I am working on Altera DE3 board with Strartix III FPGA. Verilog part of my design is capturing LVDS data from the HSTC Ports and deserializing the 8 channels of data on port. two channels (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Long time no reply. Ill try to explain the prob in plain words.

How do i fetch data into NIOS from 8 channels where each channel has 12 bits/sample. Let us say that sampling rate for now is 25 Mega Samples per second. these 8 channels are output of a verilog module.

Do i need to make an SOPC block of verilog module and then use 8 FIFOs (Plus some DMA Controller ???) to connect to NIOS. any help will be appriciated.