Inter path competition
Inter path competition results in timing drop. So My question is :
If there is a BRAM with data_out signal.
This data_out is fed to 10 modules . Just like below:
module_1(.data_in_1(data_out ))
module_2(.data_in_2(data_out ))
module_3(.data_in_3(data_out ))
......
module_10(.data_in_10(data_out ))
These paths were the critical paths and had high slack.
So, I tired using assignment editor manual logic duplication, and assigned
from:data_out
to: data_in (of all the input modules)
value: random name
but I didnt see any improvement in timing and critical paths shown were still the same. How should I dupilcate this in order to eliminate inter path competition ?
I dont want to use multiple BRAMs.If I should duplicate the logic using code, How should I do it?Because If i register the output from BRAM before sending to multiple modules. That register will have more number of fanout. So dont we end up in the same problem? Please explain me in terms of small sample code.
Thankyou