Intel fft simulation with Modelsim 10.5c starter version /Quartus prime pro 17.1/Aria10gx

Hi ShYanYewT,

Thanks for your support.

I have check the testbench generated by IP tools, I am pretty believe that testbench has installed all the modules

1, clk_bfm ,use to generate clk output

2, _rst_bfm, use to generate reset output

3, sink_bfm, with clk and reset 2 signal inputs and generate all the sink signals feed to fft IP core

4, source_bfm, with clk and reset 2 signal inputs and generate all the source signals for receiving the fft IP result from FFT IP.

I am not sure what kind of stimulus logic does customer need to add into this fully assembled testbench?

from the error information ,I guess it is just a sink and source BFM wrongly behaved.

but clk and rst BFM are working well.

Thanks

Jim