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New Contributor

1 year ago

Intel Ampcrypt Module Hierarchy

Hello, I am using ampcrypt to encrypt a design for a third party user, and have found that while the encrypted file cannot be viewed in Quartus, as plain text, or in the RTL viewer tool, when runnin...

Hdl

RichardT_altera

Super Contributor

1 year ago

I found out that to disable a warning message in standard, you can set the following pragma at the beginning of the verilog file:

// message_off <id>

So in this case, you can set

// message_off 12128

in the beginning of all the verilog files

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/enabling-or-disabling-specific-hdl-messages.html

Regards,

Richard Tan

mdidomenico3

New Contributor

1 year ago

Thanks for all the information. Just to summarize, there's no way to prevent a user from seeing entity/node names within the encrypted module in signal tap, technology viewer and timing analyzer?

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Intel Ampcrypt Module Hierarchy

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