Forum Discussion
mdidomenico3
New Contributor
New ContributorIntel Ampcrypt Module Hierarchy
Hello, I am using ampcrypt to encrypt a design for a third party user, and have found that while the encrypted file cannot be viewed in Quartus, as plain text, or in the RTL viewer tool, when runnin...
RichardT_altera
Super Contributor
Super ContributorI found out that to disable a warning message in standard, you can set the following pragma at the beginning of the verilog file:
// message_off <id>
So in this case, you can set
// message_off 12128
in the beginning of all the verilog files
Regards,
Richard Tan
mdidomenico3Thanks for all the information. Just to summarize, there's no way to prevent a user from seeing entity/node names within the encrypted module in signal tap, technology viewer and timing analyzer?
- RichardT_altera
Yes. There is no foolproof way to completely hide entity/node names within an encrypted module from tools like Signal Tap, Technology Viewer, and Timing Analyzer in Quartus. While encryption protects the RTL source code, Quartus must still synthesize the design.
Regards,
Richard Tan
