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Altera_Forum's avatar
Altera_Forum
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16 years ago

Integer used as parameter

Hi. I am using the cyclone II to on the 10 LED and 4 7segment for digital clock application.

The problem i faced are:

1. How to on the 10 LEDs(represent 0.1s)? 0.1s on 1 LED, 0,2s on 2 LEDs and continue.

The verilog code i used is:

for (i =1; i<11; i=i+1)

LED[i-1:0] <=LED[i-1:0] ;

if (i==11)

i=0;

(error: i is not constant and 5000 loops)

Is there solution to solve this instead of using case statement(long coding)?

2. I have 2 clocks (1Hz for second and 10Hz for .1second). So, i use 2 always block.

1st always block(10Hz clock) calculate the .1s and update the second segment if .1s reach 10.

if (a == 10) second_segment <= second_segment +1;

2nd always block second segment wil update the minit segment.

if (second_segment>9) second segment .....

error: multiconstand driver

Is there any way to solve this instead of combine 2 always block in one(use 10Hz clock)

The problem is difficult to distribute the job equally if combined.

Thanks a lot

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The purpose of this construct isn't understandable 

    for (i =1; i<11; i=i+1)
LED <=LED ;

    The "not constant" error is from using a variable part select, which isn't legal Verilog Syntax. A variable bit select as LED[i-1] would be allowed in contrast. But I'm under the impression, that you also misunderstood the operation of a Verilog for loop. So you may want to clarify your intentions first.

    From the code snippet, I don't see the reason for causing an infinite loop ("5000 loop iterations").

    The clock problem should be solved by a single (usually fast) clock and multiple clock enables.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Maybe you were going for something like this: 

    module my_led_module(
    input               clk_10hz,
    input               reset_n,
    output  reg    LED_A,  // 0.1S led output
    output  reg    LED_B   // 1S led output
    
);
always @(posedge clk_10hz or negedge reset_n)
    if(!reset_n) begin      
                            LED_A   <= 10'd1;
                            LED_B   <= 10'd1;
    end else begin
                            LED_A   <= {LED_A,LED_A};
        if(LED_A         LED_B   <= {LED_B,LED_B};
    end
endmodule

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    For FvM,

    5000 loops caused by the statement: if( i ==10), i =0;

    When i remove above statement, no error on 5000 loops.

    regarding multiple clock enable, can you explain more on it? i can't disable either one of the clock, because both always block have to continuos run. I might be misunderstand.

    for jakobjones

    the coding above talk on shift the led.So, i also have to use the case statement:case(i)

    1: LED = 10'd1;

    2: LED = 10'd3; and .....
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Well we're having trouble communicating here. Your last post would indicate that you just want a counter where LED proceeds 1,2,3,4...,8,9,10. But that is certainly not what your first post indicated. Why don't you list here the values that you want LED to take on in order?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    May be i din describe correctly.

    Actually i want the led to be used a .1s. When 0.1s, 1st LEDon. 0.2s, 1st and 2nd LEDs on. It continues until 1s 10 LEDs on together. and it rotates.

    Currently what i do is i use case statement(as explained above) and reg(as 0.1 counter, reach 10 it reset again)

    The problem with this coding is if i have a lot of LEDs(other application). The coding will be consuming.

    By the way, does verilog have rotate?

    Besides, i see a lot of# number in some book means delay. Is this for test bench or RTL modelling or both?

    thanks a lot
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    So like this: 

    module my_led_module(
    input               clk_10hz,
    input               reset_n,
    output  reg    LED_A,  // 0.1S led output
    output  reg    LED_B   // 1S led output
    
);
always @(posedge clk_10hz or negedge reset_n)
    if(!reset_n) begin      
                            LED_A   <= 10'd1;
                            LED_B   <= 10'd1;
    end else begin
                            LED_A   <= {LED_A,1'b1};
        if(LED_A) begin  
                            LED_A   <= 10'd1;
                            LED_B   <= {LED_B,1'b1};
            if(LED_B)    LED_B   <= 10'd1;
        end
    end
endmodule

    Jake