Honored ContributorHi everyone...
I want ask you a question, In my VHDL design I used integer type as input port and output port, I manage to compile and simulate it using quartus simulator, it goes well. But when I tried to simulate it in ModelSim, I got an error messages like this : "Failure: (vsim-3807) Types do not match between component and entity for port "in_data"." Does anyone know how to solve this problem? Thanks,... :)
Honored ContributorAre you sure that in both the entity and the component declaration the port is defined as integer ? Because it is what ModelSim tell you.
Else, can you put your code here because without it it's difficult to find the cause of the error.Honored ContributorThanks LETS...
here is my code, I make a sample :
library ieee;
use ieee.std_logic_1164.all;
entity CounTest is
port (
in_load : in std_logic;
in_data : in integer range 0 to 31;
in_clock : in std_logic;
in_ena : in std_logic;
out_count : out integer range 0 to 31
);
end CounTest;
architecture Behavior of CounTest is
signal reg : integer range 0 to 31;
begin
process(in_load, in_clock, in_ena)
begin
if (rising_edge(in_clock)) then
if (in_load = '1') then
reg <= in_data;
elsif (in_ena = '1') then
reg <= reg + 1;
end if;
end if;
out_count <= reg;
end process;
end Behavior;
Can you also put the code where this component is instantiated please.
Honored ContributorNo, there are no other files,
The CounTest is in the Top Level Design Entity... Compilation success, simulation success, but not in ModelSim. :D ... You can try it, I use Altera Quartus II version 9.1 SE.Honored ContributorYes but in ModelSim you instantiate it somewhere to simulate the input data.
Honored ContributorWell for that one,
I have Quartus generate the test bench by exporting the waveform file into *.vht file, and then in the EDA Tool Setting -> Simulation Setting, I add the *.vht file, when I execute Run EDA Simulation tool, normally waveform from Quartus simulator will be input for ModelSim simulation... do you have any idea...? Thanks...Honored ContributorOk, so can you put the vht file here please.
Honored ContributorDid you check the *.vht code? It's readable VHDL text.
Honored ContributorHere the *.vht code :
-- Copyright text cutted!
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "05/24/2010 19:08:56"
-- Vhdl Self-Checking Test Bench (with test vectors) for design : CounTest
--
-- Simulation tool : 3rd Party
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
PACKAGE CounTest_vhd_tb_types IS
-- input port types
-- output port names
CONSTANT out_count_name : STRING (1 TO 9) := "out_count";
-- n(outputs)
CONSTANT o_num : INTEGER := 1;
-- mismatches vector type
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type
SUBTYPE sample_type IS STD_LOGIC;
-- utility functions
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);
END CounTest_vhd_tb_types;
PACKAGE BODY CounTest_vhd_tb_types IS
FUNCTION std_logic_to_char (a: STD_LOGIC)
RETURN CHARACTER IS
BEGIN
CASE a IS
WHEN 'U' =>
RETURN 'U';
WHEN 'X' =>
RETURN 'X';
WHEN '0' =>
RETURN '0';
WHEN '1' =>
RETURN '1';
WHEN 'Z' =>
RETURN 'Z';
WHEN 'W' =>
RETURN 'W';
WHEN 'L' =>
RETURN 'L';
WHEN 'H' =>
RETURN 'H';
WHEN '-' =>
RETURN 'D';
END CASE;
END;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)
RETURN STRING IS
VARIABLE result : STRING(1 TO a'LENGTH);
VARIABLE j : NATURAL := 1;
BEGIN
FOR i IN a'RANGE LOOP
result(j) := std_logic_to_char(a(i));
j := j + 1;
END LOOP;
RETURN result;
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_to_char(VALUE),JUSTIFIED,field);
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
writeline(output,txt);
write(txt,string'(" Expected value = "));
write(txt,expected_value);
writeline(output,txt);
write(txt,string'(" Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
writeline(output,txt);
write(txt,string'(" Expected value = "));
write(txt,expected_value);
writeline(output,txt);
write(txt,string'(" Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
END CounTest_vhd_tb_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.CounTest_vhd_tb_types.ALL;
ENTITY CounTest_vhd_sample_tst IS
PORT (
in_clock : IN STD_LOGIC;
in_data : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
in_ena : IN STD_LOGIC;
in_load : IN STD_LOGIC;
sampler : OUT sample_type
);
END CounTest_vhd_sample_tst;
ARCHITECTURE sample_arch OF CounTest_vhd_sample_tst IS
SIGNAL tbo_int_sample_clk : sample_type := '-';
SIGNAL current_time : TIME := 0 ps;
BEGIN
t_prcs_sample : PROCESS ( in_clock , in_data , in_ena , in_load )
BEGIN
IF (NOW > 0 ps) THEN
IF (NOW > 0 ps) AND (NOW /= current_time) THEN
IF (tbo_int_sample_clk = '-') THEN
tbo_int_sample_clk <= '0';
ELSE
tbo_int_sample_clk <= NOT tbo_int_sample_clk ;
END IF;
END IF;
current_time <= NOW;
END IF;
END PROCESS t_prcs_sample;
sampler <= tbo_int_sample_clk;
END sample_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.CounTest_vhd_tb_types.ALL;
--- Continued...
The continued code is here :
ENTITY CounTest_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
out_count : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sampler : IN sample_type
);
END CounTest_vhd_check_tst;
ARCHITECTURE ovec_arch OF CounTest_vhd_check_tst IS
SIGNAL out_count_expected,out_count_expected_prev,out_count_prev : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
out_count_expected_prev <= out_count_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
out_count_prev <= out_count;
END PROCESS t_prcs_update_o_real_hist;
-- expected out_count
t_prcs_out_count_4: PROCESS
BEGIN
out_count_expected(4) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_4;
-- expected out_count
t_prcs_out_count_3: PROCESS
BEGIN
out_count_expected(3) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_3;
-- expected out_count
t_prcs_out_count_2: PROCESS
BEGIN
out_count_expected(2) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_2;
-- expected out_count
t_prcs_out_count_1: PROCESS
BEGIN
out_count_expected(1) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_1;
-- expected out_count
t_prcs_out_count_0: PROCESS
BEGIN
out_count_expected(0) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_0;
-- Set trigger on real/expected o/ pattern changes
t_prcs_trigger_e : PROCESS(out_count_expected)
BEGIN
trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;
t_prcs_trigger_r : PROCESS(out_count)
BEGIN
trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;
t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;
VARIABLE last_out_count_exp : STD_LOGIC_VECTOR(4 DOWNTO 0) := "UUUUU";
VARIABLE on_first_change : trackvec := "1";
BEGIN
WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
AND sampler'EVENT;
IF (debug_tbench = '1') THEN
write(txt,string'("Scanning pattern "));
write(txt,i);
writeline(output,txt);
write(txt,string'("| expected "));write(txt,out_count_name);write(txt,string'(" = "));write(txt,out_count_expected_prev);
writeline(output,txt);
write(txt,string'("| real "));write(txt,out_count_name);write(txt,string'(" = "));write(txt,out_count_prev);
writeline(output,txt);
i := i + 1;
END IF;
IF ( out_count_expected_prev /= "XXXXX" ) AND (out_count_expected_prev /= "UUUUU" ) AND (out_count_prev /= out_count_expected_prev) AND (
(out_count_expected_prev /= last_out_count_exp) OR
(on_first_change(1) = '1')
) THEN
throw_error("out_count",out_count_expected_prev,out_count_prev);
num_mismatches(0) <= num_mismatches(0) + 1;
on_first_change(1) := '0';
last_out_count_exp := out_count_expected_prev;
END IF;
trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;
t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;
t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 1000000 ps;
total_mismatches := num_mismatches(0);
IF (total_mismatches = 0) THEN
write(txt,string'("Simulation passed !"));
writeline(output,txt);
ELSE
write(txt,total_mismatches);
write(txt,string'(" mismatched vectors : Simulation failed !"));
writeline(output,txt);
END IF;
WAIT;
END PROCESS t_prcs_endsim;
END ovec_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.CounTest_vhd_tb_types.ALL;
ENTITY CounTest_vhd_vec_tst IS
END CounTest_vhd_vec_tst;
ARCHITECTURE CounTest_arch OF CounTest_vhd_vec_tst IS
-- constants
-- signals
SIGNAL in_clock : STD_LOGIC;
SIGNAL in_data : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL in_ena : STD_LOGIC;
SIGNAL in_load : STD_LOGIC;
SIGNAL out_count : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sampler : sample_type;
COMPONENT CounTest
PORT (
in_clock : IN STD_LOGIC;
in_data : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
in_ena : IN STD_LOGIC;
in_load : IN STD_LOGIC;
out_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT CounTest_vhd_check_tst
PORT (
out_count : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sampler : IN sample_type
);
END COMPONENT;
COMPONENT CounTest_vhd_sample_tst
PORT (
in_clock : IN STD_LOGIC;
in_data : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
in_ena : IN STD_LOGIC;
in_load : IN STD_LOGIC;
sampler : OUT sample_type
);
END COMPONENT;
BEGIN
i1 : CounTest
PORT MAP (
-- list connections between master ports and signals
in_clock => in_clock,
in_data => in_data,
in_ena => in_ena,
in_load => in_load,
out_count => out_count
);
-- in_clock
t_prcs_in_clock: PROCESS
BEGIN
LOOP
in_clock <= '0';
WAIT FOR 10000 ps;
in_clock <= '1';
WAIT FOR 10000 ps;
IF (NOW >= 1000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_in_clock;
-- in_ena
t_prcs_in_ena: PROCESS
BEGIN
in_ena <= '0';
WAIT FOR 20000 ps;
in_ena <= '1';
WAIT FOR 280000 ps;
in_ena <= '0';
WAIT FOR 20000 ps;
in_ena <= '1';
WAIT FOR 280000 ps;
in_ena <= '0';
WAIT FOR 20000 ps;
in_ena <= '1';
WAIT;
END PROCESS t_prcs_in_ena;
-- in_load
t_prcs_in_load: PROCESS
BEGIN
in_load <= '0';
WAIT FOR 40000 ps;
in_load <= '1';
WAIT FOR 20000 ps;
in_load <= '0';
WAIT FOR 260000 ps;
in_load <= '1';
WAIT FOR 20000 ps;
in_load <= '0';
WAIT FOR 280000 ps;
in_load <= '1';
WAIT FOR 20000 ps;
in_load <= '0';
WAIT;
END PROCESS t_prcs_in_load;
-- in_data
t_prcs_in_data_4: PROCESS
BEGIN
in_data(4) <= '0';
WAIT;
END PROCESS t_prcs_in_data_4;
-- in_data
t_prcs_in_data_3: PROCESS
BEGIN
in_data(3) <= '0';
WAIT FOR 600000 ps;
in_data(3) <= '1';
WAIT FOR 300000 ps;
in_data(3) <= '0';
WAIT;
END PROCESS t_prcs_in_data_3;
-- in_data
t_prcs_in_data_2: PROCESS
BEGIN
in_data(2) <= '1';
WAIT FOR 300000 ps;
in_data(2) <= '0';
WAIT FOR 300000 ps;
in_data(2) <= '1';
WAIT;
END PROCESS t_prcs_in_data_2;
-- in_data
t_prcs_in_data_1: PROCESS
BEGIN
in_data(1) <= '0';
WAIT FOR 600000 ps;
in_data(1) <= '1';
WAIT;
END PROCESS t_prcs_in_data_1;
-- in_data
t_prcs_in_data_0: PROCESS
BEGIN
in_data(0) <= '0';
WAIT FOR 300000 ps;
in_data(0) <= '1';
WAIT FOR 600000 ps;
in_data(0) <= '0';
WAIT;
END PROCESS t_prcs_in_data_0;
tb_sample : CounTest_vhd_sample_tst
PORT MAP (
in_clock => in_clock,
in_data => in_data,
in_ena => in_ena,
in_load => in_load,
sampler => sampler
);
tb_out : CounTest_vhd_check_tst
PORT MAP (
out_count => out_count,
sampler => sampler
);
END CounTest_arch;
