Integer type port

Thanks LETS...

here is my code, I make a sample :

 
library ieee;
use ieee.std_logic_1164.all;
 
entity CounTest is
port (
    in_load : in std_logic;
    in_data : in integer range 0 to 31;
    in_clock : in std_logic;
    in_ena : in std_logic;
    out_count : out integer range 0 to 31
);
end CounTest;
 
architecture Behavior of CounTest is
    signal reg : integer range 0 to 31;
begin
    process(in_load, in_clock, in_ena)
 
    begin
         if (rising_edge(in_clock)) then
              if (in_load = '1') then
                     reg <= in_data;
              elsif (in_ena = '1') then
                     reg <= reg +  1;
              end if;
         end if;
         out_count <= reg;
     end process;
end Behavior;

This code is synthesizeable and simulateble in Quartus Simulator, but when I pass it to ModelSim := Tools Menu => Run EDA Simulation Tool => EDA RTL Simulation. The ModelSim won't simulate it, it generate error message instead...

Any idea for what happen and solution?

Thanks...