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-- Copyright text cutted!
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "05/24/2010 19:08:56"
-- Vhdl Self-Checking Test Bench (with test vectors) for design : CounTest
--
-- Simulation tool : 3rd Party
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
PACKAGE CounTest_vhd_tb_types IS
-- input port types
-- output port names
CONSTANT out_count_name : STRING (1 TO 9) := "out_count";
-- n(outputs)
CONSTANT o_num : INTEGER := 1;
-- mismatches vector type
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type
SUBTYPE sample_type IS STD_LOGIC;
-- utility functions
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);
END CounTest_vhd_tb_types;
PACKAGE BODY CounTest_vhd_tb_types IS
FUNCTION std_logic_to_char (a: STD_LOGIC)
RETURN CHARACTER IS
BEGIN
CASE a IS
WHEN 'U' =>
RETURN 'U';
WHEN 'X' =>
RETURN 'X';
WHEN '0' =>
RETURN '0';
WHEN '1' =>
RETURN '1';
WHEN 'Z' =>
RETURN 'Z';
WHEN 'W' =>
RETURN 'W';
WHEN 'L' =>
RETURN 'L';
WHEN 'H' =>
RETURN 'H';
WHEN '-' =>
RETURN 'D';
END CASE;
END;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)
RETURN STRING IS
VARIABLE result : STRING(1 TO a'LENGTH);
VARIABLE j : NATURAL := 1;
BEGIN
FOR i IN a'RANGE LOOP
result(j) := std_logic_to_char(a(i));
j := j + 1;
END LOOP;
RETURN result;
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_to_char(VALUE),JUSTIFIED,field);
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
writeline(output,txt);
write(txt,string'(" Expected value = "));
write(txt,expected_value);
writeline(output,txt);
write(txt,string'(" Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
writeline(output,txt);
write(txt,string'(" Expected value = "));
write(txt,expected_value);
writeline(output,txt);
write(txt,string'(" Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
END CounTest_vhd_tb_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.CounTest_vhd_tb_types.ALL;
ENTITY CounTest_vhd_sample_tst IS
PORT (
in_clock : IN STD_LOGIC;
in_data : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
in_ena : IN STD_LOGIC;
in_load : IN STD_LOGIC;
sampler : OUT sample_type
);
END CounTest_vhd_sample_tst;
ARCHITECTURE sample_arch OF CounTest_vhd_sample_tst IS
SIGNAL tbo_int_sample_clk : sample_type := '-';
SIGNAL current_time : TIME := 0 ps;
BEGIN
t_prcs_sample : PROCESS ( in_clock , in_data , in_ena , in_load )
BEGIN
IF (NOW > 0 ps) THEN
IF (NOW > 0 ps) AND (NOW /= current_time) THEN
IF (tbo_int_sample_clk = '-') THEN
tbo_int_sample_clk <= '0';
ELSE
tbo_int_sample_clk <= NOT tbo_int_sample_clk ;
END IF;
END IF;
current_time <= NOW;
END IF;
END PROCESS t_prcs_sample;
sampler <= tbo_int_sample_clk;
END sample_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.CounTest_vhd_tb_types.ALL;
--- Continued...
