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ENTITY CounTest_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
out_count : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sampler : IN sample_type
);
END CounTest_vhd_check_tst;
ARCHITECTURE ovec_arch OF CounTest_vhd_check_tst IS
SIGNAL out_count_expected,out_count_expected_prev,out_count_prev : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
out_count_expected_prev <= out_count_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
out_count_prev <= out_count;
END PROCESS t_prcs_update_o_real_hist;
-- expected out_count
t_prcs_out_count_4: PROCESS
BEGIN
out_count_expected(4) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_4;
-- expected out_count
t_prcs_out_count_3: PROCESS
BEGIN
out_count_expected(3) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_3;
-- expected out_count
t_prcs_out_count_2: PROCESS
BEGIN
out_count_expected(2) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_2;
-- expected out_count
t_prcs_out_count_1: PROCESS
BEGIN
out_count_expected(1) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_1;
-- expected out_count
t_prcs_out_count_0: PROCESS
BEGIN
out_count_expected(0) <= 'X';
WAIT;
END PROCESS t_prcs_out_count_0;
-- Set trigger on real/expected o/ pattern changes
t_prcs_trigger_e : PROCESS(out_count_expected)
BEGIN
trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;
t_prcs_trigger_r : PROCESS(out_count)
BEGIN
trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;
t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;
VARIABLE last_out_count_exp : STD_LOGIC_VECTOR(4 DOWNTO 0) := "UUUUU";
VARIABLE on_first_change : trackvec := "1";
BEGIN
WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
AND sampler'EVENT;
IF (debug_tbench = '1') THEN
write(txt,string'("Scanning pattern "));
write(txt,i);
writeline(output,txt);
write(txt,string'("| expected "));write(txt,out_count_name);write(txt,string'(" = "));write(txt,out_count_expected_prev);
writeline(output,txt);
write(txt,string'("| real "));write(txt,out_count_name);write(txt,string'(" = "));write(txt,out_count_prev);
writeline(output,txt);
i := i + 1;
END IF;
IF ( out_count_expected_prev /= "XXXXX" ) AND (out_count_expected_prev /= "UUUUU" ) AND (out_count_prev /= out_count_expected_prev) AND (
(out_count_expected_prev /= last_out_count_exp) OR
(on_first_change(1) = '1')
) THEN
throw_error("out_count",out_count_expected_prev,out_count_prev);
num_mismatches(0) <= num_mismatches(0) + 1;
on_first_change(1) := '0';
last_out_count_exp := out_count_expected_prev;
END IF;
trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;
t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;
t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 1000000 ps;
total_mismatches := num_mismatches(0);
IF (total_mismatches = 0) THEN
write(txt,string'("Simulation passed !"));
writeline(output,txt);
ELSE
write(txt,total_mismatches);
write(txt,string'(" mismatched vectors : Simulation failed !"));
writeline(output,txt);
END IF;
WAIT;
END PROCESS t_prcs_endsim;
END ovec_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.CounTest_vhd_tb_types.ALL;
ENTITY CounTest_vhd_vec_tst IS
END CounTest_vhd_vec_tst;
ARCHITECTURE CounTest_arch OF CounTest_vhd_vec_tst IS
-- constants
-- signals
SIGNAL in_clock : STD_LOGIC;
SIGNAL in_data : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL in_ena : STD_LOGIC;
SIGNAL in_load : STD_LOGIC;
SIGNAL out_count : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL sampler : sample_type;
COMPONENT CounTest
PORT (
in_clock : IN STD_LOGIC;
in_data : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
in_ena : IN STD_LOGIC;
in_load : IN STD_LOGIC;
out_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT CounTest_vhd_check_tst
PORT (
out_count : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sampler : IN sample_type
);
END COMPONENT;
COMPONENT CounTest_vhd_sample_tst
PORT (
in_clock : IN STD_LOGIC;
in_data : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
in_ena : IN STD_LOGIC;
in_load : IN STD_LOGIC;
sampler : OUT sample_type
);
END COMPONENT;
BEGIN
i1 : CounTest
PORT MAP (
-- list connections between master ports and signals
in_clock => in_clock,
in_data => in_data,
in_ena => in_ena,
in_load => in_load,
out_count => out_count
);
-- in_clock
t_prcs_in_clock: PROCESS
BEGIN
LOOP
in_clock <= '0';
WAIT FOR 10000 ps;
in_clock <= '1';
WAIT FOR 10000 ps;
IF (NOW >= 1000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_in_clock;
-- in_ena
t_prcs_in_ena: PROCESS
BEGIN
in_ena <= '0';
WAIT FOR 20000 ps;
in_ena <= '1';
WAIT FOR 280000 ps;
in_ena <= '0';
WAIT FOR 20000 ps;
in_ena <= '1';
WAIT FOR 280000 ps;
in_ena <= '0';
WAIT FOR 20000 ps;
in_ena <= '1';
WAIT;
END PROCESS t_prcs_in_ena;
-- in_load
t_prcs_in_load: PROCESS
BEGIN
in_load <= '0';
WAIT FOR 40000 ps;
in_load <= '1';
WAIT FOR 20000 ps;
in_load <= '0';
WAIT FOR 260000 ps;
in_load <= '1';
WAIT FOR 20000 ps;
in_load <= '0';
WAIT FOR 280000 ps;
in_load <= '1';
WAIT FOR 20000 ps;
in_load <= '0';
WAIT;
END PROCESS t_prcs_in_load;
-- in_data
t_prcs_in_data_4: PROCESS
BEGIN
in_data(4) <= '0';
WAIT;
END PROCESS t_prcs_in_data_4;
-- in_data
t_prcs_in_data_3: PROCESS
BEGIN
in_data(3) <= '0';
WAIT FOR 600000 ps;
in_data(3) <= '1';
WAIT FOR 300000 ps;
in_data(3) <= '0';
WAIT;
END PROCESS t_prcs_in_data_3;
-- in_data
t_prcs_in_data_2: PROCESS
BEGIN
in_data(2) <= '1';
WAIT FOR 300000 ps;
in_data(2) <= '0';
WAIT FOR 300000 ps;
in_data(2) <= '1';
WAIT;
END PROCESS t_prcs_in_data_2;
-- in_data
t_prcs_in_data_1: PROCESS
BEGIN
in_data(1) <= '0';
WAIT FOR 600000 ps;
in_data(1) <= '1';
WAIT;
END PROCESS t_prcs_in_data_1;
-- in_data
t_prcs_in_data_0: PROCESS
BEGIN
in_data(0) <= '0';
WAIT FOR 300000 ps;
in_data(0) <= '1';
WAIT FOR 600000 ps;
in_data(0) <= '0';
WAIT;
END PROCESS t_prcs_in_data_0;
tb_sample : CounTest_vhd_sample_tst
PORT MAP (
in_clock => in_clock,
in_data => in_data,
in_ena => in_ena,
in_load => in_load,
sampler => sampler
);
tb_out : CounTest_vhd_check_tst
PORT MAP (
out_count => out_count,
sampler => sampler
);
END CounTest_arch;
