Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Instantiation of one module disturbing other module functionality

Hello,

Am using Cyclone V device (5CSEBA5U23). I written verilog code for ADC module and it is instantiated in top module,its working well... When i have added other module which for reading the encoder data, my ADC module behavior changed. when i commented encoder module instantiate, ADC module is working well. For ADC Module and Encoder module no signals are in common.

How can i solve the problem?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Have you checked the timing of your design? The quick way is to look at Compilation Reports in Quartus under the section "TimeQuest Timing Analyzer". Is it getting worse when you instantiate both modules?