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Altera_Forum
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11 years ago

Instantiation of one module disturbing other module functionality

Hello, Am using Cyclone V device (5CSEBA5U23). I written verilog code for ADC module and it is instantiated in top module,its working well... When i have added other module which for reading t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Have you checked the timing of your design? The quick way is to look at Compilation Reports in Quartus under the section "TimeQuest Timing Analyzer". Is it getting worse when you instantiate both modules?