Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP

Hi Adzim,

I think we may find the root cause, that is the DDR timing constraint can not meet because the PHY's PLL reference clock pin is not the same I/O bank as the PHY's.

We try to use another DLL to derive a 50M clock with the 25M clock input, and then use the 50M derived clock to drive the DDR controller with the DDR's PLL refence clock frequency setting of 100M, the DDR reading/writing has no problem. We observed that the MEM_CK is 150M which is our expectation (that means the wrong clock frequency configuration cheats the DDR3 controller generator).

So, the testing result shows that DDR can not run with 300M frequency if the PLL reference clock input pin is not located at the I/O bank as PHY's. But we are not sure that if the conclusion is correct or not. Would you like to help us to confirm this? If so, we will change the 25M clock input pin location.

Thanks!

Scott