Forum Discussion
ScottHu2021
New Contributor
New ContributorInstantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP
Dear,
We are develop an application with FPGA 5CEFA5F23C8 based on Quartus Prime Standard 18.1. One problem occurred during instantiating DDR3 controller IP core：
Our external memory is a DDR3...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Scott,
I think that the EMIF Debug Toolkit had a conflict with the design file whereby the targeting device is not compatible.
Maybe you should verify the link file is corrects for the device.
With the PLL reference clock frequency setting of 100M, I used oscilloscope to measure the frequency of memory interface clock "MEM_CK" and find the clock is 75M . It seems reasonable, because in our DDR controller configuration, memory clock frequency is : 300MHz, PLL reference clock frequency is 100MHz, rate on avalon_mm interface: full. If the PLL reference clock is given an 25M external clock, the MEM_CK should be 75M (25M * 3 ?)). Isn't it?
Yes, I think so.
Regards,
Adzim
