Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP

Hi Adzim,

Currently, only the following configuration can make DDR3 reading/writing work:

1. Set the "PLL reference clock frequency" in the "PHY Settings" to 100M (actually, I think it should be 25M); The 100M clock is the system clock derived by a PLL;

2. But while instantiating the DDR controller， we connect the clk_25m to the .pll_ref_clk as following.

ddrc ddrc_u
(
.pll_ref_clk ( clk_25m),
.global_reset_n ( pll_lock ),
.soft_reset_n ( pll_ddr_lock ),
.afi_clk ( afi_clk ),
.afi_half_clk ( ),
.afi_reset_n ( afi_reset_n ),
.afi_reset_export_n ( afi_reset_export_n ),
.mem_a ( mem_a ),
.mem_ba ( mem_ba ),
.mem_ck ( mem_ck ),
.mem_ck_n ( mem_ck_n ),
.mem_cke ( mem_cke ),
.mem_cs_n ( mem_cs_n ),
.mem_dm ( mem_dm ),
.mem_ras_n ( mem_ras_n ),
.mem_cas_n ( mem_cas_n ),
.mem_we_n ( mem_we_n ),
.mem_reset_n ( mem_reset_n ),
.mem_dq ( mem_dq ),
.mem_dqs ( mem_dqs ),
.mem_dqs_n ( mem_dqs_n ),
.mem_odt ( mem_odt ),
.avl_ready_0 ( w_adc_avl_rdy ),
.avl_burstbegin_0 ( w_adc_avl_bb ),
.avl_addr_0 ( w_adc_avl_addr ),
.avl_rdata_valid_0 ( ),
.avl_rdata_0 ( ),
.avl_wdata_0 ( w_adc_avl_data ),
.avl_read_req_0 ( 1'b0 ),
.avl_write_req_0 ( w_adc_avl_wr ),
.avl_size_0 ( 1'b1 ),
.avl_be_0 ( 4'hF ),
.avl_ready_1 ( w_gpif_avl_rdy ),
.avl_burstbegin_1 ( w_gpif_avl_bb ),
.avl_addr_1 ( w_gpif_avl_addr ),
.avl_rdata_valid_1 ( w_gpif_avl_rvld ),
.avl_rdata_1 ( w_gpif_avl_data ),
.avl_wdata_1 ( ),
.avl_read_req_1 ( w_gpif_avl_rd ),
.avl_write_req_1 ( 1'b0 ),
.avl_size_1 ( 1'b1 ),
.avl_be_1 ( 4'hF ),
.mp_cmd_clk_0_clk ( clk_100m ),
.mp_cmd_reset_n_0_reset_n ( pll_lock ),
.mp_cmd_clk_1_clk ( clk_100m ),
.mp_cmd_reset_n_1_reset_n ( pll_lock ),
.mp_rfifo_clk_0_clk ( clk_100m ),
.mp_rfifo_reset_n_0_reset_n ( pll_lock ),
.mp_wfifo_clk_0_clk ( clk_100m ),
.mp_wfifo_reset_n_0_reset_n ( pll_lock ),
.local_init_done ( local_init_done ),
.local_cal_success ( local_cal_success ),
.local_cal_fail ( local_cal_fail ),
.oct_rzqin ( oct_rzqin ),
.pll_mem_clk ( ),
.pll_write_clk ( ),
.pll_locked ( pll_ddr_lock ),
.pll_write_clk_pre_phy_clk ( ),
.pll_addr_cmd_clk ( ),
.pll_avl_clk ( ),
.pll_config_clk ( ),
.pll_mem_phy_clk ( ),
.afi_phy_clk ( ),
.pll_avl_phy_clk ( )
);

clk_25m is the output of the entity ALTCLKCTRL, because in our hardware design, the 25M clock (from external oscillator ) input pin is not placed in the the address/command bank of DDR3 controller, so I use the ALTCLKCTRL' output (its input is the external 25M clock) as the pll_ref_clk of the DDR3 controller:

25M clock from external oscillator => Clock Control Block => DDR controller PLL reference clock.

With this configuration, DDR3 can work.

But the problem is that: if 25M clock is used as the PLL reference clock of DDR3 controller, the "PLL reference clock frequency" in the "PHY Settings" should be set to 25M but not 100M.

Another question is that the usage of "25M clock from external oscillator => Clock Control Block => DDR controller PLL reference clock." is correct or not.

Any suggestion is appreciated!

Scott