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Yogesh
Occasional Contributor
Occasional ContributorInstantiation of 9x9 multipliers in cyclone V GT FPGA?
I have instantiated 96 8x8 multipliers as below each input width of 8bits , and output of 16 bits as below: genvar i;
generate
for(i=0; i<96 ; i=i+1) begin : mult_instan
lp_mult lp_mult_component...
CheepinC_altera
Regular Contributor
Regular ContributorThanks for your help. For your information, I have notified the SW team on the new case to expedite the routing.
