Forum Discussion

Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Instantiation of 9x9 multipliers in cyclone V GT FPGA?

I have instantiated 96 8x8 multipliers as below each input width of 8bits , and output of 16 bits as below: genvar i; generate for(i=0; i<96 ; i=i+1) begin : mult_instan lp_mult lp_mult_component...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

For your information, as I look into your design, I notice that there seems to be multiple LogicLock regions which are overlapping with each other. I have removed all the regions and then create a new region with only 210 DSP block. The design can pass Fitter and result in 210 DSPs utilization. I have sent the updated QAR to you through email.

Regarding your Q2 and Q3 which is specific to LogicLock, I believe we might need the SW expert to further assist. Since I am unable to duplicate a case (not sure why, but believe due to access issue), would you mind to open a new case in this Forum with title specific to LogicLock. You may then let me know the case number so that I could help to expedite the routing.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

  • Yogesh's avatar
    Yogesh
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi Chee Pin,

    I have opened the new case as 'specific to logic lock'. Its case number is as below:

    04620545

    Thankyou,

    regards,

    Yogesh