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Yogesh
Occasional Contributor
Occasional ContributorInstantiation of 9x9 multipliers in cyclone V GT FPGA?
I have instantiated 96 8x8 multipliers as below each input width of 8bits , and output of 16 bits as below: genvar i;
generate
for(i=0; i<96 ; i=i+1) begin : mult_instan
lp_mult lp_mult_component...
CheepinC_altera
Regular Contributor
Regular ContributorHi,
For your information, I have attached a simple test design with 3 instances of 8x8 lpm_mult and use LogicLock to force packing into a single DSP block for your reference. You may refer to it and then apply to your own design. You may start with smaller amount of multiplier and then slowly expand the logiclock region.
Note that generally the recommendation would be to let Fitter to perform auto-fitting for your design instead of using LogicLock to pack the DSP. Fitter will select the right resources to fit your design.
Please let me know if there is any concern. thank you.
YogeshOccasional Contributor
Occasional Contributorthankyou, will look into it
