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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Instantiation of 9x9 multipliers in cyclone V GT FPGA?

I have instantiated 96 8x8 multipliers as below each input width of 8bits , and output of 16 bits as below: genvar i; generate for(i=0; i<96 ; i=i+1) begin : mult_instan lp_mult lp_mult_component...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

As I understand it, you are inquiring why Fitter is using 48 DSP blocks instead of 32 DSP blocks to implement your design with 96 8x8 multipliers. Based on my understanding, by default, if there are sufficient DSP resources, Fitter will optimize the resource usage for better performance instead of packing all into minimum amount of DSP blocks. If you are attempting to pack your design into limited number of DSP blocks, you can try to use logic lock to force your design into a region with limited DSP resources to see to force Fitter to pack the multipliers.

Please let me know if there is any concern. Thank you.

Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thankyou.

But since I am wasting the resources, I want to force the fitter to use only 32 DSPs instead of 48 DSPs .

1) How can I use logic lock in quartus , to force fitter use limited DSPs?

2) What might be the performance in terms of frequency in both cases(32 DSPs and 48 DSPs) , if I force fitter to use limited DSPs?