Instantiate VHDL Generics with Verilog code (for testbench)

Defparam is explicitly forbidden in the Modelsim User Manual for instantiating VHDL inside a Verilog testbench:

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Generic Associations

Generic associations are provided via the module instance parameter value list. List the values

in the same order that the generics appear in the entity. Parameter assignment to generics is not

case sensitive.

The defparam statement is not allowed for setting generic values.

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