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Honored ContributorInstantiate VHDL Generics with Verilog code (for testbench)
Hello everybody. When I instanciate inputs and outpus of a verilog code with verilog testbench I use following structure: name_modu...
Altera_ForumHonored Contributor
Honored ContributorDefparam is explicitly forbidden in the Modelsim User Manual for instantiating VHDL inside a Verilog testbench:
--- Quote Start --- Generic Associations Generic associations are provided via the module instance parameter value list. List the values in the same order that the generics appear in the entity. Parameter assignment to generics is not case sensitive. The defparam statement is not allowed for setting generic values. --- Quote End ---
