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Altera_Forum's avatar
Altera_Forum
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13 years ago

Instance Abgiguous

I want to instantiate 4 Low Latency PHYs each with a different frequencies. I tried 4 separate mega-function edits, but Quartus complains about multiple instances; ie, it sees the same megafunction in 4 directories and dumps. There should be a way of specifying the instance path, but I am just not seeing it.

The error is (12179): Instance xxx is ambiguous

with Error (12180): Instance could be xxx in file ...1

Error (12180): Instance could be xxx in file ...2

Error (12180): Instance could be xxx in file ...3

Error (12180): Instance could be xxx in file ...4

You get the idea. Any suggestions?

Thanks

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Easiest way is to go into the megawizard top level file and rename the module name

    for example, you could number the phy

    module x_ll_phy

    module x_ll_phy_2

    module x_ll_phy_3

    module x_ll_phy_4

    then when you instantiate it in your hdl just use that module name

    note, everytime you edit the megafunction using the megawizard, it will revert to the original module name
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I am getting the same error as in the first post: "Instance xxx is ambiguous". I am using multiple DSP Builder modules, that compile into different user libraries to overcome identical VHDL file names from DSP Builder Signal Compiler. Renaming each (automatically created) entity is not feasible - because this needs to be done after each re-compile from DSPB.

    Any ideas to get rid of this error?

    I already checked the way using .qxp packages ("top_qxp_export" available in this forum), it works well, but then you loose possibility to access design nodes withing DSP-Builder system from top-level, e.g. when using signal tap analyzer.

    Any of your comments are appreciated - Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    why not you post the part of the code (eg. how you instantiate those modules) here and see if we can help.

    i've no problems instantiating several same modules in a code, i can even use loop to instantiate repeated modules.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Structure is as follows:

    module1.mdl converts into module1.qip, containing all HDL source files from DSP-Builder/Signal Compiler (Export HDL...)

    module1.ipx

    module2.mdl converts into module2.qip, containing all HDL source files from DSP-Builder (same as above)

    module2.ipx

    both .qip and .ipx files are added to Files list in Quartus, beside all other files (top level, sdc, etc)

    all .vhd files called in the qip-files got synthesis switch added (done by a batch conversion, can be done more or less automatically)

    --synthesis library my_lib_mod1 or

    --synthesis library my_lib_mod2 (for module 2 related source files)

    But there are still some .v files that have same name (and entity), bringing up Error message as described in previous post.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    oh no. some high level design tool that i don't really like to use. you might wanna consult some DSP-builder expert in other forum. or some matlab simulink experts.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I do not expect that this issue is related to DSP-Builder/Simulink itself. It is natural that automatically generated HDL from multiple modules results in equal file and entity names that later come together in top level design. So (I hope) there should be another more simplistic methode to allow Quartus to deal with such situation. Just assigning different library names (to avoid having everything in default 'work' library) for different modules is apparently not sufficient.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Just tried solution from souvir (see Thread "Multiple DSP Builder designs with conflicting VHDL" from NickG - sorry, unable to post links as having <5 posts here) to put all HDL Files generated by DSPBuilder into the same directory. Files with unique names and entities are being overwritten - but I checked for those and they are identical - so no matter at all.

    Including the --library <my_lib> switch in each source file of separate modules, Quartus will compile without issues :)

    So this is a work-around if anyone wants to avoid using boxed .qxp modules, allowing access to all design nodes within DSP Builder system. If qxp blocks are ok, just use top_qxp_export as described in Altera Wiki.