I am getting the same error as in the first post: "Instance xxx is ambiguous". I am using multiple DSP Builder modules, that compile into different user libraries to overcome identical VHDL file names from DSP Builder Signal Compiler. Renaming each (automatically created) entity is not feasible - because this needs to be done after each re-compile from DSPB.
Any ideas to get rid of this error?
I already checked the way using .qxp packages ("top_qxp_export" available in this forum), it works well, but then you loose possibility to access design nodes withing DSP-Builder system from top-level, e.g. when using signal tap analyzer.
Any of your comments are appreciated - Thanks!