Instance Abgiguous

Structure is as follows:

module1.mdl converts into module1.qip, containing all HDL source files from DSP-Builder/Signal Compiler (Export HDL...)

module1.ipx

module2.mdl converts into module2.qip, containing all HDL source files from DSP-Builder (same as above)

module2.ipx

both .qip and .ipx files are added to Files list in Quartus, beside all other files (top level, sdc, etc)

all .vhd files called in the qip-files got synthesis switch added (done by a batch conversion, can be done more or less automatically)

--synthesis library my_lib_mod1 or

--synthesis library my_lib_mod2 (for module 2 related source files)

But there are still some .v files that have same name (and entity), bringing up Error message as described in previous post.