Inserting SignalTap without re-routing design

Hi Rysc

So I finally got signal tap in a separate partition. Basically it required 3 compilations. Here is what I did.

Compile 1:

I had compiled the design and decided to tap it for debugging.

Compile 2:

I created a partition for my design.

In Project Navigator window I clicked on Hierarchy tab. Selected the module that I wanted to preserve. Right clicked on it and selected Design Partition-->Set as Design Partition.

Now I could see my module in Design Partition Window. I changed its Netlist type to Post-Fit.

Compile 3:

Now I added a signal tap to the project.

I can see the design being preserved in the reports now.

Question

Is it possible to view Pre-synthesis nodes in signal tap using this method (Im trying it out right now)? The signals that I want to see are not visible in Post fit mode.

Thanks for your help

You shouldn't have to do Compile 2. Note that your design is in a partition called Top automatically, so as long as you don't mind preserving the entire design(besides SignalTap, which is automatically not preserved), then just set that Top to Post-Fit.

When you do create a partition, your entire design has to be resynthesized and refit from scratch, so you can't preserve the stuff from Compile 1. Remember that a partition is synthesized independently of other partitions, and by doing so, it's placement info can be preserved. When you create a new partition in Compile 2, the partition information in Top changes too, so that has to be resynthesized and refit as well as your new partition. Skipping Compile 2 and just setting Top to Post-Fit will preserve everything and should work.

As for looking at pre-synthesis nodes, the answer is no, not if you want to preserve placement and routing. Those presynthesis nodes generally don't exist anymore. Think of a 2 input AND gate feeding a 3 input OR gate in your RTL. After synthesis, these may all be merged into a single LUT. If you want to tap the output of the AND gate, it doesn't exist anymore and the only way to get at it is to go back and resynthesize the design so the AND gate is the output of a LUT, but if you resynthesize then the node names change(and changes in one area of synthesis can affect other areas) so the post-fit information no longer applies.

I think I know what the problem was. I'm using Qsys in my design and as a first step I generate my design files. This makes it necessary for me to set the design partition property of my Top partition to Ignore source files changes.

Once I did this I could get signal tap to work. But not every time.

During the routing stage, my fitter attempts to route a few times and then it fails. I have confirmed this by compiling the design with no/just one signal in my .stp file versus a bunch of signals. It works in the former case but not in the latter.

Please see the attachment for log messages. Is there a work around for this?

thanks

Sorry, not sure. I haven't seen that before. Since one of the partitions is locked down it is possible to have something that is just impossible, although looking at your routing utilization it doesn't look bad at all. Maybe tapping other nodes will get around it or provide enough information to proceed?

One other idea is to follow the same flow but do Rapid Recompile, if it's available. It depends on version of Quartus, device, etc. Check under Processing -> Start -> Rapid Recompile.