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Altera_Forum
Honored Contributor
Honored ContributorInserting SignalTap without re-routing design
I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signa...
Altera_ForumHonored Contributor
Honored ContributorI think I know what the problem was. I'm using Qsys in my design and as a first step I generate my design files. This makes it necessary for me to set the design partition property of my Top partition to Ignore source files changes.
Once I did this I could get signal tap to work. But not every time. During the routing stage, my fitter attempts to route a few times and then it fails. I have confirmed this by compiling the design with no/just one signal in my .stp file versus a bunch of signals. It works in the former case but not in the latter. Please see the attachment for log messages. Is there a work around for this? thanks
