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Altera_Forum
Honored Contributor
Honored ContributorInserting SignalTap without re-routing design
I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signa...
Altera_ForumHonored Contributor
Honored ContributorSorry, not sure. I haven't seen that before. Since one of the partitions is locked down it is possible to have something that is just impossible, although looking at your routing utilization it doesn't look bad at all. Maybe tapping other nodes will get around it or provide enough information to proceed?
One other idea is to follow the same flow but do Rapid Recompile, if it's available. It depends on version of Quartus, device, etc. Check under Processing -> Start -> Rapid Recompile.
