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Markgel's avatar
Markgel
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4 years ago
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inout PIO value change

Have an Avalon inout PIO register connected to PCIe Bar addr space. When changing the "in" buffer - it doesn't affect the output buffer, but if reading PIO from PCIe bar the value does changed to the updated one according the "in" buffer (the "out" buffer remains "outdated"). How to make the "in" buffer propagate to "out" buffer, without initiating a write from PCIe bar? (Don't use NIOS, using only HW).

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    4 years ago

    Hi Mark,


    Pertaining to the question earlier on the output buffer does not reflect the changing of the input buffer, it is an expected behavior. The hardware logic in the PIO is separate for reading and writing the data register. Reading the data register returns the value present on the input ports (if present). Writing data affects the value driven to the output ports (if present). These ports are independent; reading the data register does not return previously-written data.


    For the self clearing bit, you may select "Enable individual bit setting/clearing" when you generate the PIO IP. This option is available for the output register only. When this option is turned on, two additional registers—outset and outclear—are implemented. You can use these registers to specify the output bit to set and clear.


    Thanks

    Best regards,

    KhaiY


8 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    When changing the "in" buffer - it doesn't affect the output buffer, but if reading PIO from PCIe bar the value does changed to the updated one according the "in" buffer (the "out" buffer remains "outdated"). How to make the "in" buffer propagate to "out" buffer, without initiating a write from PCIe bar? (Don't use NIOS, using only HW).

    I am sorry, I do not understand the questions. Do you mind elaborating further in details or giving example?


    Thanks

    Best regards,

    KhaiY


  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


    Best regards,

    KhaiY


    • Markgel's avatar
      Markgel
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi

      Have a PIO buffer created with platform designer, connected to PCIe bar. Need to implement self clearing bit - PC writes "1", then next clock (or couple of clocks) this bit have to be self cleared. Please advice how to implement.

      BR,

      Mark.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Mark,


    1) Which device you are using? Are you using P-tile or L-Tile / H-tile?

    2) Are you using Avalon MM interface or Avalon ST interface?

    3) Is the PCIe a Endpoint or Root port?

    4) Are you trying to configure the BAR address space?

    5)Regarding the self clearing bit, may I know which bit is this? What is the function of this bit? Is the 'bit' in memory read/write TLP or configuration TLP?

    6) It is mentioned that the PIO buffer is connected to PCIe BAR. May I know the PCIe signal name that connects to this PIO buffer?

    7) PC write 1. Can you describe how does the PC write 1 and through which interface/signal? Do you mean resetting something in the PCIe?


    Thanks

    Best regards,

    KhaiY


  • Markgel's avatar
    Markgel
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi KhaiY

    There is some clarifications:

    1) Currently using cyclone IV, but planning to implement this on cyclone 10 and Stratix V when boards are ready.

    2) Currently using MM, but OK with ST for Cyclone 10 and Stratix V (not significant)

    3) PCIe end point hard IP

    4) bar is configured and PIO have an address in bar address space which possible to write via PCIe and PIO value is changed

    5) using write from PCIe to memory bit (PIO in reality)

    6) Its memory data 32 bit, which is accessible from PCIe for write. Enough to do MSB as self clearing

    7) No, just standard write from PCIe to Bar 0 address which PIO connected via platform designer Avalon MM interface.

    BR,

    Mark.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Mark,


    Pertaining to the question earlier on the output buffer does not reflect the changing of the input buffer, it is an expected behavior. The hardware logic in the PIO is separate for reading and writing the data register. Reading the data register returns the value present on the input ports (if present). Writing data affects the value driven to the output ports (if present). These ports are independent; reading the data register does not return previously-written data.


    For the self clearing bit, you may select "Enable individual bit setting/clearing" when you generate the PIO IP. This option is available for the output register only. When this option is turned on, two additional registers—outset and outclear—are implemented. You can use these registers to specify the output bit to set and clear.


    Thanks

    Best regards,

    KhaiY


  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    Best regards,

    KhaiY