Forum Discussion
inout PIO value change
- 5 years ago
Hi Mark,
Pertaining to the question earlier on the output buffer does not reflect the changing of the input buffer, it is an expected behavior. The hardware logic in the PIO is separate for reading and writing the data register. Reading the data register returns the value present on the input ports (if present). Writing data affects the value driven to the output ports (if present). These ports are independent; reading the data register does not return previously-written data.
For the self clearing bit, you may select "Enable individual bit setting/clearing" when you generate the PIO IP. This option is available for the output register only. When this option is turned on, two additional registers—outset and outclear—are implemented. You can use these registers to specify the output bit to set and clear.
Thanks
Best regards,
KhaiY
Hi Mark,
1) Which device you are using? Are you using P-tile or L-Tile / H-tile?
2) Are you using Avalon MM interface or Avalon ST interface?
3) Is the PCIe a Endpoint or Root port?
4) Are you trying to configure the BAR address space?
5)Regarding the self clearing bit, may I know which bit is this? What is the function of this bit? Is the 'bit' in memory read/write TLP or configuration TLP?
6) It is mentioned that the PIO buffer is connected to PCIe BAR. May I know the PCIe signal name that connects to this PIO buffer?
7) PC write 1. Can you describe how does the PC write 1 and through which interface/signal? Do you mean resetting something in the PCIe?
Thanks
Best regards,
KhaiY