Forum Discussion
New Contributorinout PIO value change
Hi Mark,
Pertaining to the question earlier on the output buffer does not reflect the changing of the input buffer, it is an expected behavior. The hardware logic in the PIO is separate for reading and writing the data register. Reading the data register returns the value present on the input ports (if present). Writing data affects the value driven to the output ports (if present). These ports are independent; reading the data register does not return previously-written data.
For the self clearing bit, you may select "Enable individual bit setting/clearing" when you generate the PIO IP. This option is available for the output register only. When this option is turned on, two additional registers—outset and outclear—are implemented. You can use these registers to specify the output bit to set and clear.
Thanks
Best regards,
KhaiY
New ContributorHi KhaiY
There is some clarifications:
1) Currently using cyclone IV, but planning to implement this on cyclone 10 and Stratix V when boards are ready.
2) Currently using MM, but OK with ST for Cyclone 10 and Stratix V (not significant)
3) PCIe end point hard IP
4) bar is configured and PIO have an address in bar address space which possible to write via PCIe and PIO value is changed
5) using write from PCIe to memory bit (PIO in reality)
6) Its memory data 32 bit, which is accessible from PCIe for write. Enough to do MSB as self clearing
7) No, just standard write from PCIe to Bar 0 address which PIO connected via platform designer Avalon MM interface.
BR,
Mark.
