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Markgel's avatar
Markgel
Icon for New Contributor rankNew Contributor
5 years ago
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inout PIO value change

Have an Avalon inout PIO register connected to PCIe Bar addr space. When changing the "in" buffer - it doesn't affect the output buffer, but if reading PIO from PCIe bar the value does changed to th...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi Mark,


    Pertaining to the question earlier on the output buffer does not reflect the changing of the input buffer, it is an expected behavior. The hardware logic in the PIO is separate for reading and writing the data register. Reading the data register returns the value present on the input ports (if present). Writing data affects the value driven to the output ports (if present). These ports are independent; reading the data register does not return previously-written data.


    For the self clearing bit, you may select "Enable individual bit setting/clearing" when you generate the PIO IP. This option is available for the output register only. When this option is turned on, two additional registers—outset and outclear—are implemented. You can use these registers to specify the output bit to set and clear.


    Thanks

    Best regards,

    KhaiY


KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY


Markgel's avatar
Markgel
Icon for New Contributor rankNew Contributor
5 years ago

Hi

Have a PIO buffer created with platform designer, connected to PCIe bar. Need to implement self clearing bit - PC writes "1", then next clock (or couple of clocks) this bit have to be self cleared. Please advice how to implement.

BR,

Mark.